A Bi-CMOS electronic photonic integrated circuit quantum light detector

Complimentary metal-oxide semiconductor (CMOS) integration of quantum technology provides a route to manufacture at volume, simplify assembly, reduce footprint, and increase performance. Quantum noise–limited homodyne detectors have applications across quantum technologies, and they comprise photonics and electronics. Here, we report a quantum noise–limited monolithic electronic-photonic integrated homodyne detector, with a footprint of 80 micrometers by 220 micrometers, fabricated in a 250-nanometer lithography bipolar CMOS process. We measure a 15.3-gigahertz 3-decibel bandwidth with a maximum shot noise clearance of 12 decibels and shot noise clearance out to 26.5 gigahertz, when measured with a 9–decibel-milliwatt power local oscillator. This performance is enabled by monolithic electronic-photonic integration, which goes below the capacitance limits of devices made up of separate integrated chips or discrete components. It exceeds the bandwidth of quantum detectors with macroscopic electronic interconnects, including wire and flip chip bonding. This demonstrates electronic-photonic integration enhancing quantum photonic device performance.

Photonic integrated circuits (PIC) are a compelling approach to develop quantum technology [1,2] and they underpin proposed architectures for optical quantum computing [3,4].CMOS compatible PIC platforms, such as silicon on insulator photonics [5,6], offer paths to scaling up the manufacture of photonic devices for quantum technology in commercial foundries.This may prove critical in the construction of universal quantum computers, because the scale and performance required of components to build quantum computers is beyond anything yet constructed in information technologies [3].
Since initial experiments with silicon quantum photonic circuits [7,8], CMOS compatibility for electronicphotonic integration has been a clear goal for quantum photonics.This is because it would enable integration at scale of components generating and utilising quantum states of light with the required high performance classical readout and control electronics.But to date, the development of foundry ePIC platforms [6,9] has been driven by the performance demands of classical applications, with demonstrations including 56 GB/s direct detection receivers [10] and 128 Gb/s coherent receivers [11] for fibre optics telecommunciations, and coherent detector arrays with active pixel amplifiers for 3D imaging [12].
Here we demonstrate electronic-photonic integration can be applied to enhance quantum technologies.We report integration in one monolithic ePIC chip (Figure 1) of all the electronics and silicon photonics needed for homodyne detection of quantum optical signatures [13].The detector has a measured 3-dB bandwidth of 19.8 ± 0.1 GHz and a maximum measured shot noise clearance of 15 dB.By extrapolating the measured clearance, we infer shot noise limited performance beyond the bandwidth of our analysis equipment, measuring more than 10 dB at 26.5 GHz.* Jonathan.Matthews@bristol.ac.ukHomodyne detectors can measure weak signals by interfering them with a local oscillator at an optical beamsplitter.The resulting interference is observed in the subtraction of photocurrents from a pair of photodiodes placed at the two beamsplitter outputs.This subtraction current requires amplification, and when the amplification electronics are of sufficiently low noise, the homodyne detector is sensitive enough to reveal quantum noise signatures in the input.This is quantified by the clearance between optical shot noise and the electronic noise of the detector.Quantum technology applications of homodyne detectors include squeezed-light-enhanced gravitational wave detection [14,15], quantum state tomography [13], measuring continuous variables cluster states [16,17] for quantum computing and for continuous variables quantum communication [18].

Waveguide integrated beamsplitters have been used
for homodyne detection with silica-on-silicon [19] and lithium niobate PICs [20].In silicon-on-insulator photonics, on-chip germanium p-i-n photodiodes have been integrated with waveguides and interfaced with discrete amplifier electronics for quantum random number generation and coherent state tomography [21], and as a chip-scale receiver for continuous variables quantum key distribution [22].In these cases, the detector bandwidths were limited to respectively ∼100 MHz and ∼10 MHz by discrete electronics, mounted on printed circuit boards (PCB).Consequently, micro-electronic amplifiers were wirebonded to silicon PICs, and the resulting detectors demonstrated 3-dB bandwidths of 1.7 GHz [23] and 1.5 GHz [24] -these detectors were respectively used to measure squeezing over a 9 GHz bandwidth and observe shot noise clearance out to 20 GHz.
A remaining limiting factor in the speed of these detectors is the 20 fF -100 fF capacitance overhead of the electrical bondpad interconnection [25], that interfaces the PIC with the integrated electronics.Flip-chip interfaces introduce similar capacitance overheads, and so also restrict the possible bandwidth of hybrid integration us- The photonics include grating couplers (G), mode converters, strip waveguides, a multi-mode interference coupler beamsplitter (MMI) and germanium-silicon photodiodes (PDs).The electronics are a two-stage TIA design.The first transistor (Q1) forms a common-emitter shunt-feedback TIA; the second, (Q2), constitutes a 50 Ω output buffer amplifier.RF, RC, RE label the feedback, load and emitter resistors.b A 3D illustration of connections between components using three of the five metal layers in the SG25H5 EPIC process [9] used to fabricate the device.Light grey indicates silicon-on-insulator, dark grey indicates bulk silicon.c A microscope image of the detector illustrates scale.AMP labels the TIA and buffer amplifier stages.This device fits within a 80 µm × 220 µm footprint.
ing macroscopic interconnects.In order to increase bandwidth further, monolithic integration is required.
The reported single-chip homodyne detector is illustrated in Figure 1.It was designed and characterised in-house with fabrication outsourced to the Leibniz Institute for High Performance Microelectronics (IHP).We chose IHP's SG25H5 EPIC process, which features a 250 µm silicon node, germanium-based photodiodes with f 3dB > 60 GHz and vertically integrated heterojunction bipolar transistors (HBTs) for RF applications using 250 nm lithography with a specified transition frequency f T = 220 GHz and a breakdown voltage of 1.7 V [9].The RF performance of these HBTs is comparable to the lateral n-channel MOSFET transistors in references [26][27][28].This is due to the vertical carrier transport of the HBT, meaning speed is less dependent on the lithography resolution allowing vertical bipolar transistors to outper-form NMOS devices at the same process node [29].The HBTs are integrated in the same front-end-of-line process as the silicon-on-insulator waveguides and active optical components, such as modulators and photodiodes.This approach removes all bondpad and packaging parasitics, with connections between photonics and electronics made in the metal interconnect layers of the back-end-of-line (BEOL).
The IHP fabrication process begins with a SOI wafer optimised for photonics, with a 220nm silicon layer thickness and a 2um thick buried oxide layer.A 'local-SOI' approach is employed in which SOI regions that are to be used for BiCMOS devices are etched down to the silicon substrate.Bulk silicon is selectively regrown epitaxially in these regions and is subsequently planarised using chemical-mechanical planarisation.Patterning of electronic and photonic structures is conducted in parallel and the electrical contacts to the photodiodes and transistors are made with the same process step [30].Devices are then connected through a single shared BEOL with five metal layers.
The transimpedance amplifier (TIA) used consists of a HBT common-emitter amplifier in shunt-feedback configuration, followed by a 50 Ω buffer amplifier for interfacing with standard radio frequency (RF) test equipment (see Figure 1).The bandwidth of a single-stage shuntfeedback TIA with an ideal second-order Butterworth response is given by [31] where C in is the total capacitance at the amplifier input, R F is the feedback resistance and A 0 f A is the gainbandwidth product.A monolithic design reduces C in by minimising the stray capacitance between the photodiodes and amplifier due to bondpads or other wiring related sources.This comes in addition to the already low capacitance associated with integrated photodiodes and high performance HBTs -integrated photodiodes with capacitances as low as 9 fF and amplifier input capacitance of order 100 fF have been reported [32,33].This is in stark contrast to the packaging and layout associated parasitic capacitance on a PCB of up to tens of picofarads [21,34].Eq. 1 demonstrates the fundamental trade-off between the detector bandwidth and the transimpedance gain from the subtraction photocurrent to output voltage.Larger transimpedance gains are desirable to ensure the detector noise lies above the noise floor of any subsequent equipment and provide the maximum shot noise clearance when a local oscillator field is applied.However, the practically usable R F and achievable bandwidth are constrained by the total input capacitance and the gain-bandwidth product.In the case of a single transistor amplifier, the gain-bandwidth product is proportional to the transistor transition frequency, f T via A 0 f 0 ≈ C I /C L f T , where C I /C L is ratio of transistor input and load capacitances [35].
The input-referred current noise power spectral density is given by, where I C is the HBT collector current, β is the DC current gain, g m is the transistor transconductance and R b the base resistance [35].The first two terms are white noise terms, specifically the feedback resistor Johnson noise and base current shot noise, respectively.The latter terms scale quadratically with frequency to a limit set by the photodiode junction capacitance and total capacitance, including parasitics, presented to the amplifier input.
The amplifier is implemented with two n-p-n transistors as shown in Figure 1 a, the design of which is provided as part of the SG25H5 EPIC process development kit (PDK).The transition frequency f T is maximised for a particular collector current density-for our collector area, this corresponds to an optimal bias current I C of 4.5 mA.Achieving the optimal collector current requires careful tuning of the biasing resistors R C and R E for a given transimpedance gain R F .We perform lumped element SPICE simulations of the amplifier to optimise resistances with V cc1 = 2.2 V and V cc2 = 1.7 V dictated by the transistor breakdown voltage.The chosen resistors are R F = 600 Ω, R c = 250 Ω and R E = 35 Ω where the feedback resistance has been chosen to provide sufficient clearance above the fundamental thermal noise floor of the 50 Ω termination resistor in RF test equipment.Photonic layout was performed using IPKISS and Cadence Virtuoso.Simulations, electronic design, layout and post-layout electronic simulations were performed using Cadence Virtuoso using PDK SPICE models provided by IHP.
The gain spectrum of an ideal shunt-feedback TIA is that of a second-order Butterworth filter, given by where A 2 0 is the absolute gain at zero frequency.The second stage buffer operates as a unit gain amplifier and can be assumed to have a bandwidth approximately equal to the transistor transition frequency [35].
A 3D model and a microscope image of the detector is shown in Figure 1 b & c.A 20 µm trace connects the photodiodes subtraction signal the the amplifier input.Our parasitic extraction simulations estimate the parasitic capacitance of this interface at 7 fF, compared with 105 fF when simulating a single bondpad at the amplifier input.The ePIC is bonded to a purpose-made PCB designed for high-frequency operation.Vertical silicon capacitors (Murata UWSC, 1 nF) are used on the PCB for power supply decoupling on transistor and photodiode biases.The ePIC itself contains additional vertical metal-insulator-metal capacitors located next to each component for additional supply filtering (not shown in Figure 1 a).The TIA output wirebond is kept short to minimise parasitic inductance.
We characterise the bandwidth, common-mode rejection ratio (CMRR), linearity and responsivity of the device.Light is coupled into the chip using grating couplers, and multimode interferometers (MMIs) are used as beamsplitters.A continuous-wave (CW) tuneable laser (PurePhotonics PPCL550) at 1550 nm and amplified with an erbium-doped fibre amplifier (PriTel), is used as a local oscillator (LO).A variable optical attenuator (VOA, OzOptics) adjusts LO power.Noise measurements are recorded using a Keysight N9020B MXA electronic spectrum analyser (ESA) with a 26.5 GHz bandwidth.Photodiode and transistor biases are supplied from sourcemeters (Keysight U2722A & Keithley 2450) which are also used to monitor the two individual photocurrents of the diodes.We compare measured photocurrents when injecting LO at the top and bottom MMI ports, finding a splitting ratio of 42:58 transmission to reflection.This imbalance results in a net photocurrent at the amplifier input and excess electronic noise at the amplifier output (see Appendix).We offset this effect by reducing the bias on the bottom photodiode until the photocurrents are matched, with a maximum difference of 80 µA at the maximum LO power.This reduces the quantum efficiency of the bottom diode to 72% of its maximum value.
The top and bottom photodiodes are each reverse biased at 2 V and -0.3 V, respectively, relative to an amplifier input voltage of 0.9 V.The transistor supplies, V cc1 and V cc2 (see Figure 1 a), are set to 2.2 V and 1.65 V. To account for signal loss from PCB transmission lines and coaxial cables, we measure S21 parameters of a PCB co-planar waveguide test structure and the coaxial cable used in the experiment using a Keysight N5225A network analyser.
We perform a bandwidth measurement by optimising coupling at maximum power using the monitored photocurrent, then recording a series of spectra on the ESA as the VOA adjusts the input power from 13.5 dBm to -26.5 dBm.We also record the ESA displayed average noise level (DANL, the intrinsic ESA noise) for later subtraction from the data.All spectra are recorded at 100 kHz RBW over a 26.5 GHz span.The results of this are plotted in Figure 2. By fitting the detector response to a second-order Butterworth response, we obtain a 3-dB bandwidth of 19.8 ± 0.1 GHz.As the clearance of the detector extends beyond the bandwidth of our ESA, we estimate the shot noise bandwidth using Eq. 2. We fit the clearance of the detector with A/(B + Cf 2 ) + 1 where A describes the optical shot noise, B the white noise terms of Equation 2 and C the latter frequency dependent terms (see Appendix).The fit suggests that the shot noise clearance extends far beyond the measured bandwidth, vanishing beyond 100 GHz.In practice we anticipate the photodiode transit time bandwidth to become limiting [36].The dashed line shows a fit to Eq 3 and gives a 3 dB bandwidth of 19.8 ± 0.1 GHz.b, PSD of the detector normalised to the amplifier electronic noise.c, Raw and electronic noise subtracted detector noise variance at 1 GHz against total photocurrent.The horizontal line represents the electronic noise level.A linear fit to the data (dashed) indicates a gradient of 0.99 ± 0.01, demonstrating the presence of vacuum shot noise up to a maximum clearance of 15 dB.
Grating coupler losses are measured using grating-tograting test structures that we included on the ePIC chip.This yields an average of approximately 4.0 dB per coupler.We characterise the photodiode responsivity by comparing the sum of measured photocurrents to off-chip LO power and correcting for grating coupler losses.From this, we obtain a maximum photodiode responsivity of 0.47 A/W at 2 V bias, including MMI insertion loss.

CMRR measurements are made by intensity-
)UHTXHQF\0+] 1RLVH3RZHUG%P FIG. 3. Detector common mode rejection ratio at 500 MHz.The LO power is set to generate 10 µA of total photocurrent and the noise power recorded with one or both photodiodes reverse biased.We observe a maximum of 27 dB CMRR at 500 MHz modulating the LO using an electro-optic modulator and comparing the signal with either both photodiodes biased as above, or one biased and the other disconnected to eliminate its photocurrent contribution.
The ESA is set to 10 kHz RBW and a span ±0.1% of the modulation frequency.We observe a CMRR of 27 dB at 500 MHZ (Figure 3), which is limited by the intrinsic splitting ratio of our MMI.In future devices, this value can be improved by substituting the current static MMIs with thermoelectric tuneable Mach-Zehnder interferometers [23].
An ePIC quantum light detector is reported, combining photonics and readout electronics within a 80 µm × 220 µm footprint.This was achieved thanks to the CMOS compatibility of silicon photonics, which can benefit the scalability and manufacturability of photonic quantum information processors and could be a potential necessity when considering the stringent timing limits imposed by feed-forward and delay lines [37].The detector's 19.8 ± 0.1 GHz 3-dB bandwidth is an order of magnitude greater than previous fastest demonstrations and surpasses the speed performance limits of homodyne detectors constructed from macroscopic wirebond interconnects [23].The demonstration maintained shot noise efficiencies of at least 95%.Higher gains, and thus higher efficiencies, will be possible in future devices through multi-stage amplifier designs without sacrificing bandwidth [31].Higher responsivity photodiodes have been demonstrated in silicon photonics, achieving 95% quantum efficiency with 30 GHz bandwidths in classical appliations [38], and fibre-coupling efficiencies of 95% have been observed with edge couplers [39].Incorporating such improvements will enable ePIC detectors to simultaneously meet all of the performance requirements of future quantum technologies.We believe the current detector's footprint and performance already opens application of ePIC homodyne detectors to minaturised and high speed receivers for quantum communications [18,22], higher clock rates cluster state characterisation [16,17] and large arrays of coherent receivers for continuous vari-ables photonic quantum computing [4] and photonic neural networks operating below the Landauer limit [40].
Beyond detectors, we anticipate future applications of ePICs to increase the performance of quantum device control, including increasing the number of simultaneously controlled phase shift parameters beyond O(10 2 ) in highly programmable quantum devices [41].We ex-pect the combination of minaturised readout and control within ePICs will reduce the requirements on optical delay lines for quantum technologies utilising statemeasurement and feedforward [37].This is important for large-scale implementations of quantum technology including, multiplexed sources of quantum states [42], quantum state engineering [43] and measurement-based and time-multiplexed quantum computing [4,44].

I. APPENDIX Current offset excess noise
Due to the MMI imbalance before the photodiodes, we observe a power dependent net current offset, i dif f , at the amplifier input.This results in excess electronic noise at the amplifier output which we attribute to a combination of LO relative intensity noise and the amplifier's DC current dependent gain.Figure A1 shows characterisation of the detector with symmetric 2 V reverse biases on each photodiode.

Shot noise clearance limit
The clearance of a balanced homodyne detector is described by a function of the form, where A describes the shot noise contribution and B and C represent the white noise and quadratic noise terms of Equation 2 in the main text [34].We fit this function to the measured clearance data, plotting the data and fit in Figure A2.We normalise the measured detector shot-noise response to the amplifier and spectrum analyser electronic noise to obtain the ratio of quantum to classical noise, or clearance.We extrapolate the trend beyond our 26.5 GHz measurement bandwidth through a fit to Equation 1, suggesting clearance beyond 100 GHz.

FIG. 1 .
FIG. 1.A Bi-CMOS integrated homodyne detector for measuring quantum light.a The detector schematic.The photonics include grating couplers (G), mode converters, strip waveguides, a multi-mode interference coupler beamsplitter (MMI) and germanium-silicon photodiodes (PDs).The electronics are a two-stage TIA design.The first transistor (Q1) forms a common-emitter shunt-feedback TIA; the second, (Q2), constitutes a 50 Ω output buffer amplifier.RF, RC, RE label the feedback, load and emitter resistors.b A 3D illustration of connections between components using three of the five metal layers in the SG25H5 EPIC process [9] used to fabricate the device.Light grey indicates silicon-on-insulator, dark grey indicates bulk silicon.c A microscope image of the detector illustrates scale.AMP labels the TIA and buffer amplifier stages.This device fits within a 80 µm × 220 µm footprint.

FIG. A1 .
FIG. A1.Characterisation with imbalanced photocurrents.a, PSD of the device response at different LO powers.ESA DANL, amplifier electronic noise and cable/ PCB transmission losses have been removed.We attribute the excess noise centred at 6 GHz to intensity noise from the EDFA.b, Raw (purple crosses) and electronic noise subtracted (orange pluses) noise variances against total photocurrent.Dashed lines indicate the electronic noise level and a linear fit to the data, respectively.The fit gives a gradient of 1.26 ± 0.01, indicating the presence of excess classical noise in addition to vacuum shot noise.